1. Field of the Invention
The embodiments of the invention generally relate to a system-on-chip (SOC) structure and, more particularly, to an SOC structure that allows for automated integration of multiple intellectual property (IP) and other cores, a design structure for the SOC structure and an associated method of forming the SOC structure.
2. Description of the Related Art
Systems-on-chip (SOCs) are integrated circuits that typically incorporate multiple functional cores or macros interconnected over a common system bus. The functional cores can comprise a variety of third party intellectual property (IP) cores, logic cores, memory cores, processor cores, dust logic cores and/or an input/output system core. These SOCs are becoming increasingly larger and denser with an increasing number and variety of cores. This increase in size and density inevitably results in longer turn around times (TATs) due to the complexities of integrating the many functional cores both during netlist creation and physical design. Therefore, there is a need in the art for a SOC structure and method of forming such an SOC that allows for automated integration of functional cores in an SOC in order to simplify netlist creation and physical design and, thereby minimize turn around times (TATs).